1. Field of the Invention
The present invention relates to an analyzing method and related techniques of a power distribution system, and more particularly, to an analyzing method and related techniques of effectively analyzing couplings between power ports.
2. Description of the Prior Art
In modern society, data and videos may be transmitted, processed, and stored through electronic signals. Therefore, various electronic circuits for processing electronic signals are hardware bases of modern information society.
As known by those skilled in the art, modern electronic circuits are formed on semiconductor chips through semiconductor fabrication processes. However, mechanical properties of the semiconductor chips are fragile, and therefore, the semiconductor chips have to be appropriately packed or be adhered to appropriate encapsulated circuit boards to protect the semiconductor chips. The packaged circuit boards have signal wiring to connect the chips on the packaged circuit board to the external chips or the external circuits for being a path of the chips on the packaged circuit board to communicate with the external chips or the external circuits. Similarly, the packaged circuit board has power wiring to connect the chips of the packaged circuit board to external power such as a regulator. Therefore, the chips are able to drain required bias voltages and currents through the power wiring, which is regarded as the power distribution system of the chips.
Ideally, the power wiring of the power distribution system comprises a perfect conductor capable of completely transmitting external power to the chips. However, in fact, the power wiring has parasitic inductances and parasitic resistances, and there are electrical couplings between the power wiring also. The properties of the power distribution system for transmitting power are affected by the abovementioned non-ideal factors so that the power distribution system is not able to transmit external power completely to the chips. For example, as known by those skilled in the art, while a chip outputs time-variant electronic signals, an output driving circuit of the chip has to draw a bias current for outputting electronic signals. With variations of the electronic signals, the bias current for outputting electronic signals also varies. The power distribution system accordingly transmits a time-variant bias current to an output circuit of the chip through the power wiring according to requirements of the output driving circuit. However, while the time-variant bias current is transmitted, and while the time-variant bias current flows through the power wiring, the power wiring consumes voltage of the bias current and lowers the transmitted bias voltage because of parasitic equivalent inductances on the power wiring of the power distribution system. Thereby, the effective bias voltage received by the chip is much less than the supplied voltage from the external voltage source. Such non-ideal factors affect other bias operations in the chip and result in errors. In modern chips, since a chip processes many bits of data with a high-speed and a high-frequency clock, a large plurality of output circuits of the chip is simultaneously switched for outputting time-variant electronic signals. This leads to severe variations of a total bias current of the chip so that the voltage transmitted by the power wiring is lowered more obviously. For a power distribution system, the non-ideal factors lead to a simultaneous switching noise (SSN) of the bias voltage. For manipulating the non-ideal factors of the power distribution system, the affected degrees of the power distribution system are quantified and analyzed according to the bias voltage. Therefore, a chip designer can improve the design of the circuits of the chip and the power distribution system appropriately and add appropriate compensation circuits, such as a decoupling capacitor, for overcoming the non-ideal factors of the power distribution system.
Among prior-art power distribution system analysis methods, the bias voltage degradation caused by non-ideal factors is estimated according to the equivalent inductance of a single pad. As known by those skilled in the art, a chip has a plurality of power pads and a plurality of ground pads, and both of the plurality of pads are connected to a positive terminal and a ground terminal of the bias voltage source respectively through the power wiring of the power distribution system. Assume in a pair, including a power pad and a ground pad, which may be regarded as a set of pads or a power port, an equivalent parasitic inductance Leff is parasitic to power wiring connected to both of the pads. Therefore, when the pair of pads draws a bias current I from corresponding power wiring, a voltage degradation Vd is provided on the power wiring, and the voltage degradation Vd may be denoted as: Vd=Leff*(dl/dt). In other words, the voltage degradation Vd is proportional to a time-varying rate of the inductance of the equivalent inductance Leff to a current. When there are N sets of pads in a chip and N is a positive integer, the voltage degradation caused by the non-ideal factors of the power distribution system may be denoted as N*Leff*(dl/dt) in prior art analysis methods. In other words, in prior art power distribution system analysis methods, an equivalent inductance of a single set of pads of the power distribution system is first estimated, then the equivalent inductance is utilized for estimating a total voltage degradation of all the sets of pads of the chip caused by non-ideal factors.
However, the abovementioned analysis methods have defects. The prior art analysis methods do not take the couplings between the power wiring into considerations. In the power distribution system, except for the equivalent inductance Leff provided from a self-inductance of the wiring of single set of pads, there may also be mutual inductances and parasitic capacitances between the power wiring of various sets of pads, and this affects the properties and the performance of the power distribution system, such as the voltage degradation. In prior art analysis methods, only self-inductances of the N sets of pads are summed up for estimating the performance of the power distribution system. This is not able to concretely point out the effects caused by the mutual inductances and not able to precisely estimate the performance of the power distribution system.